Successive approximation A/D converter, imaging device, endoscope, and setting method

ABSTRACT

A disclosed analog-to-digital converter includes; a sampling circuit to sample a pair of analog signals as a differential input signal; a binary capacitance holding the sampled pair of analog signals and reflecting a level of a reference signal to the analog signals through the binary capacitance to generate a pair of voltage signals; a comparator including a transistor to which the voltage signals are input, to compare one of the voltage signals with the other; a correction circuit provided previously to the comparator, to output to the comparator the pair of voltage signals in which voltage dependency of stray capacitance in the input transistor is cancelled; and a controller that successively determines a value of each bit of a digital signal corresponding to the binary capacitance based on a comparison by the comparison circuit, and reflects the value of each bit of the digital signal to the reference signal.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of PCT International Application No.PCT/JP2017/032169 filed on Sep. 6, 2017, which designates the UnitedStates, incorporated herein by reference, and which claims the benefitof priority from Japanese Patent Application No. 2016-247964, filed onDec. 21, 2016, incorporated herein by reference.

BACKGROUND

The present disclosure relates to a successive approximationanalog-to-digital (A/D) converter configured to convert an analogsignal, which is externally input, into a digital signal, an imagingdevice, an endoscope, and a setting method.

As a low power consumption analog-to-digital (A/D) converter, adifferential input asynchronous successive approximation A/D converterhas been known (for example, in “A 26 μW 8 bit 10 MS/s Asynchronous SARADC for Low Energy Radios”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.46, No. 7, pp. 1585-1596, July 2011). This successive approximation A/Dconverter holds a pair of analog signals input in a sample hold circuitas a differential input signal, and causes comparison circuit togenerate a comparison voltage signal by reflecting a reference signal inthe held analog signals through a capacitor circuit. Based on thiscomparison voltage signal, a successive-approximation logical circuitdetermines respective bit values (0 or 1) of MSB to LSB of the digitalsignal corresponding to the differential input signal according to abinary search algorithm, and feeds back the determined respective bitvalues to the reference signal.

The successive approximation A/D converter can be configured mostly witha digital circuit, without using an analog circuit, such as anoperational amplifier. Therefore, the successive approximation A/Dconverter can be implemented in a small size by using a minutecomplementary metal oxide semiconductor (CMOS) process, and can reducepower consumption. In terms of capability of reducing power consumptionand downsizing, the successive approximation A/D converter is used for asystem large scale integration (LSI) of, for example, a mobile device.

SUMMARY

According to a first aspect of the present disclosure, a successiveapproximation analog-to-digital converter is provided which includes asampling circuit configured to sample a pair of analog signals input asa differential input signal; a capacitor circuit that has a binarycapacitance configured to hold the pair of analog signals sampled by thesampling circuit, the capacitor circuit being configured to reflect asignal level of a reference signal to the pair of analog signals throughthe binary capacitance to generate a pair of voltage signals; acomparator circuit that includes an input transistor to which the pairof voltage signals are input, the comparator circuit being configured tocompare one of the pair of voltage signals with the other signal of thepair of voltage signals; a correction circuit that is provided in aprevious stage to the comparator circuit, the correction circuit beingconfigured to output the pair of voltage signals in which voltagedependency of stray capacitance in the input transistor is cancelled tothe comparator circuit; and a control circuit configured to successivelydetermine a value of each bit of a digital signal corresponding to thebinary capacitance based on a comparison result by the comparisoncircuit, and to reflect the value of each bit of the digital signal tothe reference signal.

According to a second aspect of the present invention, an imaging deviceis provided which includes the successive approximation A/D converteraccording to the first aspect; an imaging device including a pluralityof pixels that are arranged in a two-dimensional matrix, and thatreceive light input from outside to perform photoelectric conversion,and that outputs an imaging signal, wherein the imaging device includesa noise removing circuit that is arranged for each of columns of thetwo-dimensional matrix in which the pixels are arranged, the noiseremoving circuit being configured to remove a noise component includedin the imaging signal; a plurality of column source-follower buffersthat are arranged for each of the columns of the two-dimensional matrixin which the pixels are arranged, the plurality of columnsource-follower buffers being configured to and that amplify the imagingsignal from which the noise component is removed by the noise removingunit; a column selecting circuit that sequentially selects the columnsource-follower buffers to output the imaging signal; and a buffercircuit that forms a voltage follower circuit, being connected to thecolumn source-follower buffer sequentially selected by the columnselecting circuit, and that subjects a voltage of the imaging signaloutput from the column source-follower buffer to impedancetransformation, to output to the successive approximationanalog-to-digital converter.

According to a third aspect of the present invention, an endoscope isprovided which includes an imaging device according to the secondaspect; and an insertion portion insertable to a subject, the insertionportion includes the imaging device at a distal end.

According to a fourth aspect of the present invention, a setting methodthat is performed in a successive approximation analog-to-digitalconverter is provided. The successive approximation analog-to-digitalconverter includes a correction circuit that includes a sampling circuitthat samples a pair of analog signals input as a differential inputsignal; a capacitor circuit that has a binary capacitance holding thepair of analog signals sampled by the sampling circuit, the capacitorcircuit being configured to reflect a signal level of a reference signalto the pair of analog signals through the binary capacitance to generatea pair of voltage signals; a comparator circuit that includes an inputtransistor to which the pair of voltage signals are input, thecomparator circuit being configured to compare one of the pair ofvoltage signals with the other signal of the pair of voltage signals; acorrection transistor that is provided in a previous stage to thecomparator circuit, the correction transistor being configured to cancelvoltage dependency of stray capacitance in the input transistor; and abias circuit that applies a predetermined bias voltage to the correctiontransistor, the correction circuit being configured to output the pairof voltage signals to the comparator circuit; and a control circuitconfigured to successively determine a value of each bit of a digitalsignal corresponding to the binary capacitance by binary search, basedon a comparison result by the comparator circuit, and to reflect thevalue of each bit of the digital signal to the reference signal. Themethod includes setting a value of the bias voltage applied by the biascircuit; applying the bias voltage having the set value sequentially tothe correction transistor; inputting a test signal to the successiveapproximation A/D converter sequentially such that the successiveapproximation A/D converter is caused to perform A/D conversion;calculating an integral non-linearity difference of each of the outputcode based on a measurement result obtained by sequentially measuringthe output code converted at the A/D conversion; calculating respectivemaximum value and minimum value of the integral non-linearity differencefor each of the output code, based on the integral non-linearitydifference; and setting a value of the bias voltage such that adifference between absolute values of the calculated maximum values andthe calculated minimum values is reduced, and such that an average valueof the absolute values of the maximum values and the minimum values isreduced, as a value of the bias voltage to be applied by the biascircuit.

The above and other features, advantages and technical and industrialsignificance of this disclosure will be better understood by reading thefollowing detailed description of presently preferred embodiments of thedisclosure, when considered in connection with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram schematically illustrating an entireconfiguration of an endoscope system according to a first embodiment ofthe present disclosure;

FIG. 2 is a block diagram illustrating the endoscope system according tothe first embodiment of the present disclosure;

FIG. 3 is a block diagram illustrating a detailed configuration of animaging device illustrated in FIG. 2;

FIG. 4 is a circuit diagram schematically illustrating a configurationof the imaging device according to the first embodiment of the presentdisclosure;

FIG. 5 is a circuit diagram illustrating a configuration of areference-voltage generating unit according to the first embodiment ofthe present disclosure;

FIG. 6 is a circuit diagram schematically illustrating a configurationof the reference-voltage generating unit according to the firstembodiment of the present disclosure;

FIG. 7 is a circuit diagram schematically illustrating a configurationof a first analog-to-digital (A/D) converter according to the firstembodiment of the present disclosure;

FIG. 8 is a diagram illustrating a relationship of voltage dependentcharacteristics between an input capacitor of a comparison circuit andan input capacitor of a correction transistor of a correction circuitaccording to the first embodiment of the present disclosure;

FIG. 9 is a diagram illustrating an integral non-linearity (INL)characteristic of an output signal that is output by a conventionalsuccessive approximation A/D converter;

FIG. 10 is a diagram illustrating an INL characteristic of an outputsignal that is output by the first A/D converter according to the firstembodiment of the present disclosure;

FIG. 11A is a timing chart illustrating an operation of the imagingdevice according to the first embodiment of the present disclosure;

FIG. 11B is a schematic diagram in which part of the timing chart in aregion R1 in FIG. 11A is enlarged;

FIG. 12 is a circuit diagram schematically illustrating a configurationof a reference-signal generating unit according to a first modificationof the first embodiment of the present disclosure;

FIG. 13 is a circuit diagram schematically illustrating a configurationof a reference-signal generating unit according to a second modificationof the first embodiment of the present disclosure;

FIG. 14 is a circuit diagram schematically illustrating a configurationof an imaging device according to a second embodiment of the presentdisclosure;

FIG. 15 is a circuit diagram schematically illustrating a configurationof a reference-signal generating unit according to the second embodimentof the present disclosure;

FIG. 16A is a timing chart illustrating an operation of the imagingdevice according to the second embodiment of the present disclosure;

FIG. 16B is a schematic diagram in which part of the timing chart in aregion R2 in FIG. 16A is enlarged;

FIG. 17 is a circuit diagram schematically illustrating a configurationof a first A/D converting unit according to a third embodiment of thepresent disclosure;

FIG. 18 is a flowchart illustrating a method of adjusting a bias voltageof a correction circuit according to the third embodiment of the presentdisclosure;

FIG. 19A is a diagram schematically illustrating INL characteristicswhen the bias voltage (1) of the correction circuit according to thethird embodiment of the present disclosure is changed;

FIG. 19B is a diagram schematically illustrating the INL characteristicswhen a bias voltage (N) of the correction circuit according to the thirdembodiment of the present disclosure is changed; and

FIG. 19C is a diagram schematically illustrating the INL characteristicswhen a bias voltage (n) of the correction circuit according to the thirdembodiment of the present disclosure is changed.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An endoscope system that includes an endoscope having an imaging deviceat a distal end of an insertion portion to be inserted into a subject isdescribed as a form (hereinafter, “embodiment”) to implement the presentdisclosure. The embodiment is not intended to limit the presentdisclosure. Moreover, it is described giving like reference symbols tolike parts throughout the drawings. Furthermore, it is noted that thedrawings are of schematic illustration, and a relationship betweenthickness and width dimensions of respective components, a ratio of therespective components, and the like differ from those in an actualsituation. Furthermore, there can be part in which relationships indimensions or ratios differ from one another among the drawings.

First Embodiment

Configuration of Endoscope

FIG. 1 is a schematic diagram schematically illustrating an entireconfiguration of an endoscope system according to a first embodiment ofthe present disclosure. An endoscope system 1 illustrated in FIG. 1includes an endoscope 2, a transmission cable 3, a connector unit 5, aprocessor 6, a display device 7, and a light source device 8.

The endoscope 2 images an inside of a subject, having an insertionportion 100 that is part of the transmission cable 3 inserted into abody cavity of the subject, and outputs an imaging signal to theprocessor 6. Moreover, the endoscope 2 has an imaging device 20 thatimages an inside of the subject and generates the imaging signal. Theimaging device 20 is provided at a distal end portion 101 of theinsertion portion 100 that is inserted into a body cavity of a subject,which is at one end of the transmission cable 3. Furthermore, theendoscope 2 has an operation unit 4 that accepts various kinds ofoperations with respect to the endoscope 2. The operation unit 4 isprovided at a distal end portion 102 of the insertion portion 100. Theimaging signal of an internal body image imaged by the imaging device 20is output to the connector unit 5 through the transmission cable 3having length of, for example, several meters (m).

The transmission cable 3 connects the endoscope 2 and the connector unit5, and connects the endoscope 2 with the processor 6 and the lightsource device 8. Moreover, the transmission cable 3 transmits theimaging signal generated by the imaging device 20 to the connector unit5. The transmission cable 3 is constituted of a cable, an optical fiber,or the like.

The connector unit 5 is connected to the processor 6 and the lightsource device 8, and subjects the imaging signal output by the endoscope2 connected thereto to predetermined signal processing to output to theprocessor 6.

The processor 6 subjects the imaging signal input from the connectorunit 5 to predetermined image processing to output to the display device7. Moreover, the processor 6 generally controls the entire endoscopesystem 1. For example, the processor 6 performs control of switchingillumination light output by the light source device 8 or switchingimaging modes of the endoscope 2.

The display device 7 displays an image corresponding to the imagingsignal subjected to image processing by the processor 6. Moreover, thedisplay device 7 displays various kinds of information relating to theendoscope system 1. The display device 7 is constituted of a displaypanel, such as a liquid crystal display and an organicelectroluminescence (EL) display, or the like.

The light source device 8 irradiates illumination light toward a subject(subject to be imaged) from the distal end portion 101 side of theinsertion portion 100 of the endoscope 2 via the connector unit 5 andthe transmission cable 3. The light source device 8 is constituted of awhite light emitting diode (LED) that emits white light, or the like. Inthe first embodiment, a simultaneous illumination method is applied tothe light source device 8, but a frame sequential illumination method isalso applicable.

Endoscope System

Next, the endoscope system 1 is described with reference to FIG. 2,which is a block diagram illustrating the endoscope system 1.

Configuration of Endoscope

First, a configuration of the endoscope 2 is described.

The endoscope 2 illustrated in FIG. 2 includes the imaging device 20,the transmission cable 3, and the connector unit 5. The imaging device20 includes an imaging device 21 (imaging chip) and an optical system 22that forms a subject image on the imaging device 21.

The imaging device 21 includes a light receiving unit 23 having pluralpixels that are arranged in a two-dimensional matrix in column and rowdirection, that receive light from outside, and that generates andoutputs an imaging signal according to a reception light amount, areading unit 24 that sequentially reads an imaging signal that has beensubjected to photoelectric conversion by the light receiving unit 23 percolumn, a buffer unit 25 that impedance-transforms a voltage of theimaging signal sequentially read by the reading unit 24 and amplifies itto one time as large by a voltage follower to output, a reference-signalgenerating unit 26 that generates and outputs a reference signal havinga fluctuation component in phase with the imaging signal generated bythe light receiving unit 23 and used for correction processing of theimaging signal, an analog-to-digital (A/D) converter 27 that samples ananalog imaging signal output from the buffer unit 25 and a referencesignal generated by the reference-signal generating unit 26 at the sametiming, and that converts the analog signal into a digital imagingsignal to output to the outside, a timing generating unit 28 thatgenerates a timing signal based on a reference clock signal and asynchronization signal, and a hysteresis unit 29 that performs waveformshaping of the reference clock signal and the synchronization signalinput from the connector unit 5 through the transmission cable 3, andthat outputs the reference clock signal and the synchronization signalsubjected to the waveform shaping to the timing generating unit 28.Moreover, the imaging device 21 receives a power supply voltage VDD (forexample, 3.3 volts (V)) generated by a power supply unit 61 of theprocessor 6 described later through the transmission cable 3, togetherwith a ground GND. Between the power supply voltage VDD supplied to theimaging device 21 and the ground GND, a capacitor C1 for stabilizing thepower supply is provided. A detailed configuration of the imaging device21 is described later with reference to FIG. 3.

The optical system 22 is configured using multiple lenses and a prism,and forms a subject image on the light receiving unit 23 of the imagingdevice 21.

The connector unit 5 includes a pulse generating unit 51 that generatesa synchronization signal (including a horizontal synchronizing signaland a vertical synchronizing signal) indicating a start position of eachframe based on the reference clock signal (for example, clock signal of27 megahertz (MHz)) that is supplied by the processor 6 and that is tobe a reference of an operation of each component of the endoscope 2, tooutput to the timing generating unit 28 of the imaging device 20 throughthe transmission cable 3 together with the reference clock signal, asignal processing unit 52 that is configured using a field programmablegate array (FPGA), application specific integrated circuit (ASIC), orthe like, and that subjects the digital imaging signal output from theimaging device 20 through the transmission cable 3 to predeterminedimage processing, for example, nose reduction processing, to output tothe processor 6, and a power-supply-voltage generating unit 53 that isconfigured using a regulator or the like, and that generates a powersupply voltage necessary for driving the imaging device 21 from a powersupplied from the processor 6 to output to the imaging device 21.

Configuration of Processor

Next, a configuration of the processor 6 is described.

The processor 6 includes the power supply unit 61 that generates a powersupply voltage, and that supplies the generated power supply voltage VDDto the power-supply-voltage generating unit 53 of the connector unit 5together with the ground GND, a clock generating unit 62 that generatesa reference clock signal to be a reference of an operation of eachcomponent of the endoscope system 1, and that outputs the referenceclock signal to the pulse generating unit 51 of the connector unit 5, aprocessor control unit 63 that is configured using a central processingunit (CPU) or the like, and that generally controls the entire endoscopesystem 1, and an image processing unit 64 that converts the digitalimaging signal input from the endoscope 2 into an image signal byperforming image processing, such as synchronization processing, whitebalance (WB) adjustment processing, gain adjustment processing, gammacorrection processing, digital-to-analog (D/A) conversion processing,and format conversion processing, and that outputs this image signal tothe display device 7.

Configuration of Imaging Device

Next, a detailed configuration of the imaging device 21 described aboveis described. FIG. 3 is a block diagram illustrating a detailedconfiguration of the imaging device 21 illustrated in FIG. 2.

As illustrated in FIG. 3, the imaging device 21 includes the lightreceiving unit 23, the reading unit 24, the buffer unit 25, thereference-signal generating unit 26, the A/D converter 27, the timinggenerating unit 28, and the hysteresis unit 29.

The light receiving unit 23 has plural pixels that are arranged in atwo-dimensional matrix in column and row direction, and that receivelight from the outside, and that generate and output an imaging signalaccording to a reception light amount. A configuration of pixels in thelight receiving unit 23 is described in detail in FIG. 4 describedlater.

The reading unit 24 sequentially reads an imaging signal from therespective pixels of the light receiving unit 23 described later tooutput to the buffer unit 25. The reading unit 24 includes a verticalscanning unit 241 (row selecting circuit), a constant-current powersupply 242, a noise removing unit 243, a column source-follower buffer244, a horizontal scanning unit 245 (column selecting circuit), and areference-voltage generating unit 246.

The vertical scanning unit 241 applies driving signals ϕT<M> and ϕR<M>to a selected row (horizontal line)<M> (M=0, 1, 2, . . . , m−1, m) basedon the driving signal (ϕT, ϕR, and the like) input from the timinggenerating unit 28, to drive the respective pixels 230 of the lightreceiving unit 23 with the constant-current power supply 242, andthereby transfers the imaging signal and a noise signal at the time ofpixel reset to a vertical transfer line 239 (first transfer line)described later to output to the noise removing unit 243.

The noise removing unit 243 removes output variations of the respectivepixels 230 described later and the noise signal at the time of pixelreset, and outputs the imaging signal generated by photoelectricconversion in the respective pixels 230 described later to the columnsource-follower buffer 244.

The column source-follower buffer 244 holds the imaging signal fromwhich a noise is removed by the noise removing unit 243 based on thedriving signal input from the horizontal scanning unit 245, andamplifies this held imaging signal to output the amplified imagingsignal to the buffer unit 25.

The horizontal scanning unit 245 applies a driving signal ϕHCLK<N> to aselected column (vertical line)<N> (N=0, 1, 2, . . . , n−1, n) of thelight receiving unit 23 based on a driving signal (ϕHCLK) input from thetiming generating unit 28, and transfers the imaging signal generated byphotoelectric conversion in the respective pixels 230 to a horizontaltransfer line 257 described later through the noise removing unit 243and the column-source follower buffer 244, to output to the buffer unit25.

The reference-voltage generating unit 246 generates a clamping voltageVCLP of the noise removing unit 243 from the power supply voltage VDDthat is also applied to the light receiving unit 23. Details of acircuit of the reference-voltage generating unit 246 are described laterin FIG. 5.

The buffer unit 25 subjects a voltage of the imaging signal sequentiallyoutput from the column-source follower buffer 244 to impedancetransformation, and amplifies the imaging signal to one time as large bya voltage follower to output to the A/D converter 27. Details of acircuit of the buffer unit 25 are described later in FIG. 4.

The reference-signal generating unit 26 generates a reference signalhaving a fluctuation component in phase with the imaging signalgenerated by the light receiving unit 23 and used for correctionprocessing of the imaging signal, to output to the A/D converter 27.Details of a circuit of the reference-signal generating unit 26 aredescribed later in FIG. 6.

The A/D converter 27 samples an analog imaging signal output from thebuffer unit 25 and a reference signal generated by the reference-signalgenerating unit 26 at the same timing, and converts the analog imagingsignal into a digital imaging signal (Vout) to output to the outside.

The timing generating unit 28 generates various kinds of driving signalsbased on a reference clock signal and a synchronization signal inputfrom the hysteresis unit 29, to output to the reading unit 24 describedlater, the buffer unit 25, the reference-signal generating unit 26, andthe A/D converter 27.

The hysteresis unit 29 performs waveform shaping on the reference clocksignal and the synchronization signal input through the transmissioncable 3, and outputs the reference clock signal and the synchronizationsignal that have undergone this waveform shaping to the timinggenerating unit 28.

Configuration of Circuit of Imaging Device

Next, details of a circuit of the imaging device 21 described above aredescribed. FIG. 4 is a circuit diagram schematically illustrating aconfiguration of the imaging device 21.

Configuration of Pixel

First a configuration of the pixel 230 is described.

As illustrated in FIG. 4, in the light receiving unit 23 describedabove, the multiple pixels 230 are arranged in a two-dimensional matrix.Each of the pixels 230 includes a photoelectric converting device 231(photodiode), a charge converting unit 233, a transfer transistor 234(first transfer unit), a pixel resetting unit 236 (transistor), and apixel source-follower transistor 237.

The photoelectric converting device 231 photoelectric converts incidentlight to signal charge, and accumulates the signal charge. Here, anamount of the signal charge corresponds to an amount of the incidentlight. A cathode of the photoelectric converting device 231 is connectedto one end (e.g., source) of the transfer transistor 234, and an anodeis connected to the ground GND in each pixel 230.

The charge converting unit 233 is constituted of a stray diffusioncapacitance (FD), and converts an electric charge accumulated by thephotoelectric converting device 231 into a voltage.

The transfer transistor 234 transfers the electric charge from thephotoelectric converting device 231 to the charge converting unit 233.To a gate of the transfer transistor 234, a signal line to which adriving signal ϕT is supplied is connected, and to the other end (e.g.,drain), the charge converting unit 233 is connected. When the drivingsignal ϕT is supplied from the vertical scanning unit 241 through thesignal line, the transfer transistor 234 is turned into an on state, andtransfers the electric charge from the photoelectric converting device231 to the charge converting unit 233.

The pixel resetting unit 236 resets the charge converting unit 233 to beat a predetermined potential. The pixel resetting unit 236 is connectedto the power supply voltage VDD at one end, and is connected to thecharge converting unit 233 at the other end. To a gate, the signal lineto which the driving signal ϕR is supplied is connected. When thedriving signal ϕR is supplied from the vertical scanning unit 241through the signal line, the pixel resetting unit 236 is turned into anon state, and causes the charge converting unit 233 to release theaccumulated signal charge, to reset the charge converting unit 233 to beat a predetermined potential.

The pixel source-follower transistor 237 is connected to the powersupply voltage VDD (for example, 3.3 V) at one end, and is connected tothe vertical transfer line 239 at the other end. To a gate, a signalsubjected to voltage conversion (an imaging signal or a signal at thetime of reset) by the charge converting unit 233 is input. When thedriving signal ϕT is supplied to the gate of the transfer transistor 234after a selecting operation described later, an electric charge is readfrom the photoelectric converting device 231, and is subjected tovoltage conversion by the charge converting unit 233, and the pixelsource-follower transistor 237 then transfers the electric charge to thevertical transfer line 239.

One end of the constant-current power supply 242 is connected to thevertical transfer line 239, and the other end is connected to the groundGND. To a gate, a bias voltage Vbias1 is applicable. Theconstant-current power supply 242 drives the pixels 230, and let outputsof the pixels 230 be output to the vertical transfer line 239. Thesignal output to the vertical transfer line 239 is input to the noiseremoving unit 243.

Configuration of Noise Removing Unit

Next, a configuration of the noise removing unit 243 is described.

The noise removing unit 243 illustrated in FIG. 4 is arranged for eachcolumn of the respective pixels 230. Namely, the noise removing unit 243is arranged for each of the vertical transfer lines 239. The noiseremoving unit 243 includes a transfer capacitor 252 (alternating current(AC) coupling capacitor) and a clamp switch 253 (transistor). Note thatthe noise removing unit 243 functions as a clamp circuit in the firstembodiment.

One end of the transfer capacitor 252 is connected to the verticaltransfer line 239, and the other end is connected to a columnsource-follower transistor 254 of the column-source follower buffer 244described later.

One end of the clamp switch 253 is connected to a signal line to which aclamp voltage VCLP is supplied from the reference-voltage generatingunit 246, and the other end is connected to a line connecting thetransfer capacitor 252 and the column-source follower buffer 244. To agate of the clamp switch 253 (transistor), a driving signal ϕVCL isinput from the timing generating unit 28. The imaging signal input tothe noise removing unit 243 is an optical noise addition signalincluding a noise component.

In the noise removing unit 243 thus configured, the clamp switch 253 isturned into an on state when the driving signal ϕVCL is input to thegate of the clamp switch 253, and the transfer capacitor 252 is reset bythe clamping voltage VCLP supplied by the reference-voltage generatingunit 246. The imaging signal from which a noise has been removed by thenoise removing unit 243 is input to the gate of the columnsource-follower transistor 254 of the column source-follower buffer 244.Because the noise removing unit 243 does not require a samplingcapacitor, the capacitance of the transfer capacitor 252 (AC couplingcapacitor) is only necessary to have a capacitance sufficient for inputcapacitance of the column source-follower buffer 244. Furthermore,having no need for a sampling capacitor, the noise removing unit 243contributes to reduction of an occupying area in the imaging device 21.

Configuration of Column Source-Follower Buffer

Next, a configuration of the column source-follower buffer 244 isdescribed.

The column source-follower buffer 244 illustrated in FIG. 4 is providedfor each column of the respective pixels 230. Namely, the columnsource-follower buffer 244 is provided for each of the vertical transferlines 239. The column source-follower buffer 244 includes the columnsource-follower transistor 254 and a column selecting switch 255. Notethat the column source-follower buffer 244 functions as a column circuitin the first embodiment.

One end of the column source-follower transistor 254 is connected to thepower supply voltage VSS (hereinafter, “ground GND”), and the other endis connected to one end of the column selecting switch 255. To a gate ofthe column source-follower transistor 254, the imaging signal from whicha noise has been removed by the noise removing unit 243 is input.

One end of the column selecting switch 255 is connected to the other endof the column source-follower transistor 254, and the other end isconnected to the horizontal transfer line 257. The column selectingswitch 255 is configured using a transistor, and a signal line to supplya driving signal ϕHCLK<M> from the horizontal scanning unit 245 isconnected to a gate of the column selecting switch 255. The columnselecting switch 255 is turned into an on state when the driving signalϕHCLK<M> is supplied from the horizontal scanning unit 245, and theimaging signal from which a noise is removed by the noise removing unit243 is transferred to the horizontal transfer line 257. To thehorizontal transfer line 257, a horizontal resetting transistor (notillustrated) is connected. When a driving signal is input to thehorizontal resetting transistor from the timing generating unit 28, thehorizontal resetting transistor is turned into an on state, to reset thehorizontal transfer line 257.

In the column source-follower buffer 244 thus configured, when thedriving signal ϕHCLK<M> is applied to the column selecting switch 255from the timing generating unit 28 through the horizontal scanning unit245, the column selecting switch 255 is turned into an on state, and theimaging signal from which a noise has been removed by the noise removingunit 243 is sequentially input to the buffer unit 25 through thehorizontal transfer line 257.

Configuration of Buffer Unit

Next, a configuration of the buffer unit 25 is described.

The buffer unit 25 illustrated in FIG. 4 forms a voltage followercircuit along with the column source-follower buffers 244 connectedthereto, which are sequentially selected by the horizontal scanning unit245, and subjects a voltage of the input imaging signal to impedancetransformation, to output to the A/D converter 27. Specifically, thebuffer unit 25 amplifies the input imaging signal to one time as largeby the voltage follower, when the column source-follower buffers 244 aresequentially selected by the horizontal scanning unit 245, to output tothe A/D converter 27. The buffer unit 25 includes a first global circuit260 and a second global circuit 270 that are provided respectively foran odd column and an even column of the pixels 230. The first globalcircuit 260 and the second global circuit 270 function as an impedancetransforming unit.

The first global circuit 260 includes a constant-current power supply256, a switch 261, a first transistor 262, a second transistor 263, athird transistor 264, and a constant-current power supply 265.

One end of the constant-current power supply 256 is connected to thehorizontal transfer line 257, and the other end is connected to thepower supply voltage VDD. The constant-current power supply 256 reads animaging signal out to the horizontal transfer line 257. The imagingsignal read out to the horizontal transfer line 257 is input to a sourceof the first transistor 262 through the switch 261 described later. Notethat the constant-current power supply 256 functions as aconstant-current power supply in the first embodiment.

One end of the switch 261 is connected to the column selecting switch255 of the column source-follower buffer 244 through the horizontaltransfer line 257, and the other end is connected to a source of thefirst transistor 262. The switch 261 has a resistance similar to thecolumn selecting switch 255 of the column source-follower buffer 244,and is configured using, for example, a transistor. The switch 261 isarranged in the on state all the time, and connects between thehorizontal transfer line 257 and the first transistor 262.

One end (source) of the first transistor 262 is connected to the columnselecting switch 255 of the column source-follower buffer 244 throughthe switch 261 and the horizontal transfer line 257, and the other end(drain) is connected to the one end (drain) of the second transistor263, and a gate is connected to the A/D converter 27. The firsttransistor 262 is configured using a P-channel metal oxide semiconductor(PMOS).

One end (drain) of the second transistor 263 is connected to the otherend (drain) of the first transistor 262 and the gate of the firsttransistor 262, and the other end is connected to the ground GND, andthe gate is connected to the constant-current power supply 265. Thesecond transistor 263 is configured using an N-channel metal oxidesemiconductor (NMOS).

One end (drain) of the third transistor 264 is connected to theconstant-current power supply 265 (second constant-current powersupply), and the other end (source) is connected to the ground GND, andthe gate is connected to the constant-current power supply 265.

The first global circuit 260 thus configured forms a voltage followercircuit along with the column source-follower buffers 244 (column sidecircuit) of an odd column connected thereto, which are sequentiallyselected by the horizontal scanning unit 245, and subjects a voltage ofan imaging signal (Vin) input from the column source-follower buffer 244to impedance transformation to amplify the imaging signal to one time aslarge by voltage follower, and output the imaging signal (Vout) to theA/D converter 27.

The second global circuit 270 has the same configuration as the firstglobal circuit 260 described above, and includes the switch 261, thefirst transistor 262, the second transistor 263, the third transistor264, and the constant-current power supply 265.

The second global circuit 270 thus configured forms a voltage followercircuit along with the column source-follower buffers 244 (column sidecircuit) of an even column connected thereto, which are sequentiallyselected by the horizontal scanning unit 245, and subjects a voltage ofthe input imaging signal (Vin) to impedance transformation, and outputsthe imaging signal (Vout) amplified to one time as large by voltagefollower to the A/D converter 27.

The reference-signal generating unit 26 generates a reference signalhaving a fluctuation component in phase with the imaging signalgenerated by the pixels 230 and used for correction processing of theimaging signal, to output to the A/D converter 27. Details of a circuitof the reference-signal generating unit 26 are described later withreference to FIG. 6.

The A/D converter 27 is arranged for the odd columns and the evencolumns of the light receiving unit 23, and includes a first A/Dconverting unit 280 that converts an analog imaging signal output fromthe pixel 230 of an odd column into a digital imaging signal, to outputto the outside, and a second A/D converting unit 290 that converts ananalog imaging signal output from the pixel 230 of an even column into adigital imaging signal, to output to the outside. Details of circuits ofthe first A/D converting unit 280 and the second A/D converting unit 290are described in FIG. 7 later.

Configuration of Reference-Voltage Generating Unit

Next, a configuration of the reference-voltage generating unit 246illustrated in FIG. 3 is described. FIG. 5 is a circuit diagramillustrating a configuration of the reference-voltage generating unit246.

The reference-voltage generating unit 246 (constant-voltage-signalgenerating unit) includes a resistance divider circuit 291 constitutedof two resisters 291 a and 291 b, a switch 292 (transistor) that isdriven by a driving signal ϕVSH applied by the timing generating unit28, and a sampling capacitor 293 (capacitor) to release fromfluctuations by separating from the power supply. One end of the dividercircuit 291 is connected to VDD_A/D (for example, 3.3 V), and the otherend of the divider circuit 291 is connected to the ground GND.

The reference-voltage generating unit 246 thus configured generates aclamp voltage VCLP of the noise removing unit 243 at timing when thedriving signal ϕVSH drives by driving of the switch 292, to output tothe noise removing unit 243.

Configuration of Reference-Signal Generating Unit

Next, a detailed configuration of the reference-signal generating unit26 illustrated in FIG. 3 and FIG. 4 is described. FIG. 6 is a circuitdiagram schematically illustrating a configuration of thereference-signal generating unit 26.

The reference-signal generating unit 26 illustrated in FIG. 6 includes aresistance divider circuit 301 constituted of two resistors 301 a and301 b, a switch 302 (transistor) that drives by a driving signal appliedby the timing generating unit 28, a sampling capacitor 303 to releasefluctuations by separating from a power supply, a pixel equivalentcircuit 304, a noise-removal equivalent circuit 305, a column equivalentcircuit 306, and a buffer equivalent circuit 307.

The pixel equivalent circuit 304 forms a circuit equivalent to each ofthe pixel source-follower transistor 237 and the constant-current powersupply 242 of the pixel 230, and includes a pixel source-followertransistor 237 a and a constant-current power supply 242 a that drivesthe pixel source-follower transistor 237 a.

One end (drain) of the pixel source-follower transistor 237 a isconnected to the power supply voltage VDD, and the other end (source) isconnected to the constant-current power supply 242 a. To a gate, asignal line to which a signal transferred from the sampling capacitor303 is transferred is connected.

One end of the constant-current power supply 242 a is connected to thepixel source-follower transistor 237 a, and the other end is connectedto the ground GND (VSS). The constant-current power supply 242 a drivesthe pixel source-follower transistor 237 a, and lets an output of thepixel source-follower transistor 237 a be output to the noise-removalequivalent circuit 305.

The noise-removal equivalent circuit 305 forms a circuit equivalent tothe noise removing unit 243 described above, and includes a transfercapacitor 252 (AC coupling capacitor) and a clamp switch 253. Becausethe noise-removal equivalent circuit 305 is a circuit equivalent to thenoise removing unit 243 described above, detailed description thereof isomitted.

The column equivalent circuit 306 forms a circuit equivalent to thecolumn source-follower buffer 244 described above, and includes thecolumn source-follower transistor 254 and the column selecting switch255. Because the column equivalent circuit 306 is a circuit equivalentto the column source-follower buffer 244 described above, detaileddescription thereof is omitted.

The buffer equivalent circuit 307 forms a circuit equivalent to thefirst global circuit 260 described above, and includes theconstant-current power supply 256, the switch 261, the first transistor262, the second transistor 263, the third transistor 264, and theconstant-current power supply 265. Because the buffer equivalent circuit307 is a circuit equivalent to the first global circuit 260 describedabove, detailed description thereof is omitted.

The reference-signal generating unit 26 thus configured generates areference signal (VREF) having a fluctuation component in phase with theimaging signal generated by the pixels 230 and used for correctionprocessing of the imaging signal, to output to the A/D converter 27.

Configuration of First A/D Converter

Next, a configuration of the first A/D converting unit 280 is described.FIG. 7 is a circuit diagram schematically illustrating a configurationof the first A/D converting unit 280. Because the first A/D convertingunit 280 and the second A/D converting unit 290 has the same circuitconfiguration, only the configuration of the first A/D converting unit280 is described in the following, and description of the configurationof the second A/D converting unit 290 is omitted. Moreover, the firstA/D converting unit 280 illustrated in FIG. 7 is a successiveapproximation A/D converter and is an A/D converter of 9-bit output, butnot limited thereto, the number of output bit may be changed asappropriate. Note that as long as the first A/D converting unit 280 isan A/D converter capable of reducing power consumption, it is notnecessarily required to be a successive approximation A/D converter. Forexample, a Nyquist A/D converter is applicable.

The first A/D converting unit 280 illustrated in FIG. 7 includes asampling circuit 401, a capacitive digital-to-analog converter (DAC)circuit 402, a comparator circuit 403, a correction circuit 404, and acontrol circuit 405.

The sampling circuit 401 samples an analog imaging signal and areference signal by performing track and hold with respect to a pair ofan imaging signal (Vsignal) and a reference signal (VREF) constituting adifferential input signal at the same timing based on the clock signalCLK input from the timing generating unit 28. The sampling circuit 401includes a switch 401 a and a switch 401 b.

The switch 401 a electrically connects the first global circuit 260 andthe capacitive DAC circuit 402 when the switch 401 a is in an on state,and keeps impedance between the first global circuit 260 and thecapacitive DAC circuit 402 to a high impedance state when the switch 401a is in an off state. To the switch 401 a, an analog imaging signal isinput through a non-inverting input terminal INP. The switch 401 a holdsand samples the analog imaging signal in a capacitor unit 402 aPdescribed later at timing when the switch 401 a is switched to the offstate from the on state. The switch 401 a switches between the on stateand the off state based on the clock signal CLK input from the timinggenerating unit 28.

The switch 401 b electrically connects the reference-signal generatingunit 26 described above and the capacitive DAC circuit 402 when theswitch 401 b is in the on state, and keeps impedance between thereference-signal generating unit 26 and the capacitive DAC circuit 402into a high impedance state when the switch 401 b is in an off state. Tothe switch 401 b, the analog reference signal is input through anon-inverting input terminal INN. The switch 401 b holds and samples theanalog reference signal in a capacitor unit 402 aN described later attiming when the switch 401 b is switched to the off state from the onstate. The switch 401 b switches between the on state and the off statebased on the clock signal CLK input from the timing generating unit 28.

The capacitive DAC circuit 402 generates an analog signal based on adigital signal (DN0 to DN8, DP0 to DP8) generated by the control circuit405, and acquires a cumulative residual between a differential inputsignal and a 9-bit digital signals DO to D8 by subtracting a referencesignal (a reference signal different from the reference signal VREF)from each of the imaging signal and the reference signal sampled andheld in the sampling circuit 401. The capacitive DAC circuit 402 outputsa subtraction result that is obtained by subtracting the referencesignal from each of the imaging signal and the reference signal to thecomparator circuit 403 as the analog imaging signal (INP) and thereference signal (INN) to which the cumulative residual is reflected.The capacitive DAC circuit 402 includes the capacitor unit 402 aN, adriving unit 402 bN, a capacitor unit 402 aP, and a driving unit 402 bP.

The capacitor unit 402 aP includes an attenuation capacitor ChP andbinary capacitors COP to C8P. The attenuation capacitor ChP is connectedbetween a signal node NP corresponding to a wiring connected to theswitch 401 a and the ground GND. Moreover, the respective binarycapacitors COP to C8P are connected between the signal node NP and anoutput unit of the driving unit 402 bP. That is, the respective binarycapacitors COP to C8P are arranged such that one electrode is connectedto the signal node NP in common connection, and the other electrode isindividually connected to an output unit of inverters Q0P to Q8Pconstituting the driving unit 402 bP described later. The binarycapacitors COP to C8P are arranged corresponding to the digital signalsDP0 to DP8 that are generated by the control circuit 405. Thecapacitance values of the respective binary capacitors COP to C8P differfrom each other. For example, the capacitance value of the capacitorC(n+1)P corresponding to the digital signal DP(n+1) is two times aslarge as the capacitance value of a capacitor CnP corresponding to thedigital signal DPn (n is an integer from 0 to 7). That is, therespective capacitance values of the binary capacitors COP to C8P areweighted by binary number according to a place of respective bits of thedigital signals DP0 to DP8.

The capacitor unit 402 aN includes attenuation capacitor ChN and binarycapacitors C0N to C8N similarly to the capacitor unit 402 aP. Theattenuation capacitor ChN is connected between a signal node NN, whichcorresponds to a wiring connected to the switch 401 b, and the groundGND. Moreover, the respective binary capacitors C0N to C8N are connectedbetween the signal node NN and an output unit of the driving unit 402bN. That is, the respective binary capacitors C0N to C8N are arrangedsuch that one electrode is connected to the signal node NN in commonconnection, and the other electrode is individually connected to anoutput unit of inverters Q0N to Q8N constituting the driving unit 402 bNdescribed later. The binary capacitors C0N to C8N are arrangedcorresponding to the digital signals DN0 to DN8 that are generated bythe control circuit 405. The capacitance values of the respective binarycapacitors C0N to C8N are also by binary number, similarly to the binarycapacitors COP to C8P. Moreover, the respective capacitance values ofthe binary capacitors C0N to C8N constituting the capacitor unit 402 aNare set to same as the respective capacitance values of the binarycapacitors COP to C8P constituting the capacitor unit 402 aP.

The driving unit 402 bP includes the inverters Q0P to Q8P. To theinverters Q0P to Q8P, a power supply voltage VDD_A/D is supplied. Thismeans that amplitudes of analog signals output from the respectiveinverters Q0P to Q8P are equal to the power supply voltage VDD_A/D. Theinverters Q0P to Q8P are arranged corresponding to the digital signalsDP0 to DP8 that are generated by the control circuit 405. To each of theinverters Q0P to Q8P, each bit of the digital signals DP0 to DP8 isinput from the control circuit 405. Moreover, the respective outputunits of the inverters Q0P to Q8P are connected to the other electrodesof the binary capacitors COP to C8P.

The inverters Q0P to Q8P generate the reference signal by inverting thedigital signals DP0 to DP8 input from the control circuit 405. Thebinary capacitors COP to C8P included in the capacitor unit 402 aPsubtract the reference signal from the imaging signal Vsignal byremoving an electric charge based on the reference signal from anelectric charge based on the analog imaging signal Vsignal held in theattenuation capacitor ChP by charge redistribution. The capacitor unit402 aP outputs an analog signal VCP, which is the subtraction result, tothe comparator circuit 403.

The driving unit 402 bN includes the inverters Q0N to Q8N. To theinverters Q0N to Q8N, the power supply voltage VDD_A/D is supplied. Thismeans that amplitudes of reference signals output from the respectiveinverters Q0N to Q8N are equal to the power supply voltage VDD_A/D. Theinverters Q0N to Q8N are arranged corresponding to the digital signalsDN0 to DN8 that are generated by the control circuit 405. To each of theinverters Q0P to Q8P, each bit of the digital signals DN0 to DN8 isinput from the control circuit 405. Moreover, the respective outputunits of the inverters Q0N to Q8N are connected to the other electrodesof the binary capacitors C0N to C8N.

The inverters Q0N to Q8N generate the reference signal by inverting thedigital signals DN0 to DN8 input from the control circuit 405. Thebinary capacitors C0N to C8N included in the capacitor unit 402 aNsubtract the reference signal from the analog reference signal VREF byremoving an electric charge based on the reference signal from anelectric charge based on the analog reference signal VREF held in theattenuation capacitor ChN by charge redistribution. The capacitor unit402 aN outputs an analog signal VCN, which is the subtraction result, tothe comparator circuit 403.

The comparator circuit 403 compares the analog signal VCP based on theanalog imaging signal Vsignal and the analog signal VCN based on theanalog reference signal VREF, which are input from the capacitive DACcircuit 402, and outputs a digitals signal VIP and a digital signal VONthat indicate the comparison result according to the magnituderelationship. Specifically, the comparator circuit 403 outputs ahigh-level signal as the digital signal VOP when a signal level of theanalog imaging signal is higher than a signal level of the analogreference signal, and outputs a low-level signal as the digital signalVON. On the other hand, when a signal level of the analog imaging signalis lower than a signal level of the analog reference signal, thecomparator circuit 403 outputs a low level signal as the digital signalVOP, and outputs a high-level signal as the digital signal VON. Thecomparator circuit 403 is controlled based on an internal clock signalBIT_CLK and an inverse internal clock signal BIT_CLKb that are generatedby the control circuit 405 described later.

The correction circuit 404 is arranged in a previous stage of thecomparator circuit 403, and outputs a pair of voltage signals in which astray capacitance in the input transistor is cancelled to the comparatorcircuit 403. Specifically, the correction circuit 404 cancels a straycapacitance (gate capacitance) of the input transistor of the comparatorcircuit 403, and thereby corrects a pair of analog signal voltages inputto the comparator circuit 403 to output to the comparator circuit 403.The correction circuit 404 includes a correction transistor 404 a thatcancels a stray capacitance of the input transistor of the comparatorcircuit 403, and a bias circuit 404 b that applies a bias voltage VB tothe correction transistor 404 a. A gate terminal of the correctiontransistor 404 a is connected to the input terminal of the comparatorcircuit 403. A drain terminal and a source terminal of the correctiontransistor 404 a are connected to each other, and to the bias circuit404 b. The correction transistor 404 a constitutes a metal oxidesemiconductor (MOS) capacitor with the gate terminal, and the drain andsource terminals connected in common connection. A voltage dependence ofa capacitance of the correction transistor 404 a has an inversecharacteristic to a voltage dependence of the input transistor of thecomparator circuit 403. The voltage dependence of the correctiontransistor 404 a is described later.

The control circuit 405 functions as a successive approximation register(SAR) logical circuit, and successively determines respective bit valuesof the digital signals DP0 to DP8, and the digital signals DN0 to DN8that correspond to the digital signal VOP and the digital signal VONindicating comparison results by the comparator circuit 403 according toa binary search algorithm. The control circuit 405 supplies the digitalsignals DP0 to DP8 and the digital signals DN0 to DN8 that correspond tothe digital signal VOP and the digital signal VON, respectively, to thecapacitive DAC circuit 402. Out of these, the control circuit 405outputs the digital signals DP0 to DP8 as the digital signals DO to D8(Vout) indicating an A/D conversion result. Moreover, the controlcircuit 405 generates the internal clock signal BIT_CLK and the inverseinternal clock signal BIT_CLKb that control the comparator circuit 403,which are then supplied to the comparator circuit 403. The controlcircuit 405 is controlled based on the clock signal CLK generated by thetiming generating unit 28. The control circuit 405 generates theinternal clock signal BIT_CLK and the inverse internal clock signalBIT_CLKb in a period in which the clock signal CLK is at high level.

The first A/D converting unit 280 thus configured acquires an A/Dconversion result sequentially in 1 bit at a time from the highest levelbit (D8) toward the lowest-level bit (DO) among the digital signals DOto D8. In this A/D conversion process, the comparator circuit 403compares a signal level (voltage) of the analog imaging signal (INP) inwhich the cumulative residual up to this time is reflected and a signallevel (voltage) of the analog reference signal (INN), each time thesubtraction described above is performed by the capacitive DAC circuit402.

Moreover, a differential input range of the first A/D converting unit280 is expressed as in Equation (1) below.

$\begin{matrix}{V_{{fs},{pp}} = {2\frac{Cdac}{{Cdac} + {Ch} + {{Cst}\; 1} + {{Cst}\; 2} + {{Cst}\; 3}}{{VDD\_ A}/D}}} & (1)\end{matrix}$

Cst1 represents a stray capacitance generated between metal wirings(node wirings), Cst2 represents an input capacitance of the comparatorcircuit 403, Cst3 represents a MOS capacitance generated by thecorrection transistor 404 a, and Ch represents an attenuationcapacitance of the capacitive DAC circuit 402.

In Equation (1) above, when Ch is set so as to obtainCdac=Ch+Cst1+Cst2+Cst3, a gain factor is 1, and a full scale range isobtained. Therefore, in the first embodiment, the capacitance of thecorrection transistor 404 a is set such that the MOS capacitance valueshows a bias voltage dependence inverse to the gate capacitance of theinput transistor of the comparator circuit 403.

Characteristic of Correction Transistor

Next, the voltage dependence of the capacitance of the correctiontransistor 404 a and the capacitance of the comparator circuit 403 isdescribed. FIG. 8 is a diagram illustrating a relationship of voltagedependent characteristics between the input capacitance of thecomparison circuit 403 and the input capacitance of the correctiontransistor of the correction circuit 404. In FIG. 8, a horizontal axisrepresents an input voltage (V) of the comparator circuit 403, and avertical axis represents a capacitance. Moreover, in FIG. 8, a curve L1represents a voltage dependence characteristic of the comparator circuit403, a curve L2 represents a voltage dependence characteristic of thecorrection transistor 404 a, and a curve L3 represents a voltagedependence characteristic of the capacitance (VB parameter) of thecorrection transistor 404 a and the input capacitance of the comparatorcircuit 403 in a combined capacitance.

As illustrated in FIG. 8, the correction transistor 404 a is set suchthat the capacitance has a bias voltage dependence inverse to the gatecapacitance of the input transistor of the comparator circuit 403.Specifically, a user sets the bias voltage VB of the correctiontransistor 404 a appropriately, to make the combined capacitance of thecapacitance of the correction transistor 404 a and the input capacitanceof the comparator circuit 403 substantially flat with respect to changesin an input voltage of the comparator circuit 403. More specifically, asindicated by the curve L2, by setting the bias voltage Vb of thecorrection transistor 404 a appropriately to give a bias voltagedependence inverse to the gate capacitance of the input transistor ofthe comparator circuit 403, it is possible for a user to make thecombined capacitance of the MOS capacitance of the correction transistor404 a and the input capacitance of the comparator circuit 403substantially flat as indicated by the curve L3.

FIG. 9 is a diagram illustrating an integral non-linearity (INL)characteristic of an output signal that is output by a conventionalsuccessive approximation A/D converter. FIG. 10 shows an INLcharacteristic of an output signal that is output by the first A/Dconverting unit 280. In FIG. 9 and FIG. 10, a horizontal axis representscode, and vertical axis represents INL[a.u.]. Moreover, a curve L31 inFIG. 9 represents an INL characteristic of an output signal output bythe conventional successive approximation A/D converter, and a curve L32in FIG. 10 represents an INL characteristic of an output signal outputby the first A/D converting unit 280.

As indicated by the curve L32 in FIG. 10, in the first A/D convertingunit 280, an output signal is substantially flat, and it enables toprevent fluctuation of gain during A/D conversion. The linearity of theoutput signal is thereby maintained.

Operation of Imaging Device

Next, an operation of the imaging device 20 is described. FIG. 11A is atiming chart illustrating an operation of the imaging device 20. FIG.11B is a schematic diagram in which part of the timing chart in a regionR1 in FIG. 11A is enlarged. Referring to FIG. 11A, an explanation ismade about operations from reading an imaging signal from the pixel 230of a row <n> of the light receiving unit 23 through outputting a digitalimaging signal from the A/D converter 27. Note that, it is assumed thatonly one photoelectric converting device 231 is included in the pixel230 for convenience sake in the timing chart illustrated in FIG. 11A.When plural photoelectric converting devices 231 are included in thepixel 230 (in the case of shared pixel), an operation corresponding toone image signal line in this timing chart is repeated as many times asthe number of the photoelectric converting devices 231 included in thepixel 230. FIG. 11A illustrates, sequentially from the top most line,the driving signal ϕR, the driving signal ϕT, the driving signal ϕVCL,the driving signals SW21 to SW2 n, voltages VIN1 to VINn of the transfercapacitor 252, the output voltage Vout of the buffer unit 25, conversiontiming of the A/D converter 27, the reference clock CLK, output timingof a conversion result of the A/D converter 27, and the reference signalVREF. Furthermore, FIG. 11B illustrates, sequentially from the top mostline, the reference signal VREF, the output voltage Vout of the bufferunit 25, an operation mode of the A/D converter 27, and a differenceobtained by subtracting the reference signal VREF from the outputvoltage Vout of the buffer unit 25 (Vout−VREF).

As illustrated in FIG. 11A and FIG. 11B, first, the timing generatingunit 28 turns on the clamp switch 253 (the driving signal ϕVCL is high),turns on the pixel resetting unit 236 (the pulsed driving signal ϕR<0>is high), and turns off the transfer transistor 234 (the pulsed drivingsignal ϕT<0> is low) (time T1). With this, a noise signal includingvariations specific to the pixel 230 to be read, a noise at the time ofpixel reset, and the like is output to the vertical transfer line 239from the pixel 230. At this time, by maintaining the on state of theclamp switch 253 (the driving signal ϕVCL is high), the gate of thecolumn source-follower transistor 254 of the column source-followerbuffer 244 is to be a voltage of the clamp voltage VCLP, and thetransfer capacitor 252 is charged with VRST-VCLP.

Next, the timing generating unit 28 turns on the transfer transistor 234(the pulsed driving signal ϕT<0> is high) while the clamp switch 253 isoff (the driving signal ϕVCL is low). With this, the charge convertingunit 233 reads out a signal photoelectric-converted by the photoelectricconverting device 231 to the vertical transfer line 239 (time T2). Inthis state, an imaging signal VSIG subjected to voltage conversion bythe charge converting unit 233 is transferred to the vertical transferline 239. By this operation, the transfer capacitor 252 is charged withVCLP−(VRST1−VSIG1). Thus, the imaging signal (optical signal) from whicha noise signal is removed is output to the gate of the columnsource-follower transistor 254 of the column source-follower buffer 244through the transfer capacitor 252. The signal output to the gate of thecolumn source-follower transistor 254 of the column source-followerbuffer 244 is a signal sampled based on the clamp voltage VCLP.

Subsequently, the timing generating unit 28 turns on the columnselecting switch 255 (the driving signal SW21 is high) (time T3), andthe imaging signal Vout (VCLP−(VRST1−VSIG1) charged in the transfercapacitor 252 is thereby output to the A/D converter 27 through thecolumn source-follower buffer 244 and the first global circuit 260.

Thereafter, the timing generating unit 28 switches the column selectingswitch 255 between on and off (the driving signal SW21 is low, thedriving signal SW22 is high) (time T4), and the imaging signal Vout(VCLP−(VRST2−VSIG2) charged in the transfer capacitor 252 is therebyoutput to the A/D converter 27 through the column source-follower buffer244 and the first global circuit 260. At this time, the A/D converter 27subjects the imaging signal Vout output from the transfer capacitor 252to A/D conversion based on the reference signal VREF output from thereference-signal generating unit 26, and outputs the digital imagingsignal D1 to the outside.

Subsequently, the timing generating unit 28 switches the columnselecting switch 255 between on and off sequentially (the drivingsignals SW22 to SW2 n) (time TN), the imaging signal Vout(VCLP−(VRSTn−VSIGn) charged in the transfer capacitor 252 is therebyoutput to the A/D converter 27 sequentially through the columnsource-follower buffer 244 and the first global circuit 260. At thistime, the A/D converter 27 subjects the imaging signal Vout sequentiallyoutput from the transfer capacitor 252 to A/D conversion based on thereference signal VREF output from the reference-signal generating unit26, and sequentially outputs the digital imaging signal D2 to DN to theoutside.

By repeating the operation as described above as many time as the numberof columns of the light receiving unit 23 (or as many times as thenumber of columns to be read), a digital imaging signal in which afluctuation component in phase with the imaging signal is cancelled isoutput to the outside. Furthermore, by repeating the reading operationfor one line as many times as the number of pixel rows (or as many timesas the number of rows to be read), the imaging device 20 outputs adigital imaging signal corresponding to one frame to the outside.

Moreover, as illustrated in FIG. 11B, while the reference signal VREFand the imaging signal Vout have a common mode noise, the difference(Vout-VREF) between the output voltage Vout of the buffer unit 25 andthe reference signal VREF is not influenced by the common mode noise.The A/D converter 27 samples the output voltage Vout input from thebuffer unit 25 and the reference signal VREF generated by thereference-signal generating unit 26 at the same timing, and outputs thedigital imaging signal Vout to the outside. As a result, the A/Dconversion result is not influenced by the common mode noise.

According to the first embodiment of the present disclosure describedabove, the first global circuit 260 serves as a voltage follower circuitwhen the column source-follower buffer 244 (column side circuit) of anodd column that is sequentially selected by the horizontal scanning unit245 is connected to the first global circuit 60, performs impedancetransformation with respect to a voltage of the imaging signal (Vin)input from the column source-follower buffer 244, amplifies the imagingsignal to an amplification factor of one time as large by voltagefollower, and outputs the imaging signal (Vout). Therefore, it ispossible to make the maximum use of a level of the imaging signal outputby the column source-follower buffer 244.

Moreover, according to the first embodiment of the present disclosure,when outputting to the A/D converter 27 that operates at a power supplyvoltage lower than that of the pixel 230, the input dynamic range andthe linearity of the A/D converter 27 can be maintained.

Furthermore, according to the first embodiment, an input referred noiseof the column source-follower buffer 244 can be reduced.

Moreover, according to the first embodiment of the present disclosure,because the reference-signal generating unit 26 generates a referencesignal having a fluctuation component in phase with an imaging signalthat is generated by the pixel 230, it is possible to convert theimaging signal into a digital imaging signal to be output, in acondition practically not influenced by a common mode noise.

Furthermore, according to the first embodiment of the presentdisclosure, because a capacitor connected to the input terminal of thecomparator circuit 403 can be made substantially flat with respect tochanges in an input voltage of the comparator circuit 403, it ispossible to prevent degradation of the linearity of an output signalthat is output by the A/D converter 27.

First Modification of First Embodiment

Next, a first modification of the first embodiment of the presentdisclosure is described. The first modification of the first embodimentdiffers in a configuration of the reference-signal generating unit 26according to the first embodiment described above. In the following, aconfiguration of the reference-signal generating unit 26 according tothe first modification of the first embodiment is described. Note thatlike reference symbols are assigned to like components as the endoscopesystem 1 according to the first embodiment described above, anddescription thereof is omitted.

Configuration of Reference-Signal Generating Unit

FIG. 12 is a circuit diagram schematically illustrating a configurationof the reference-signal generating unit according to a firstmodification of the first embodiment of the present disclosure.

A reference-signal generating unit 26 a illustrated in FIG. 12 has aconfiguration in which the noise-removal equivalent circuit 305, thecolumn equivalent circuit 306, and the buffer equivalent circuit 307 areomitted from the reference-signal generating unit 26 according to thefirst embodiment described above, and includes the resistance dividercircuit 301 constituted of two resistors 301 a and 301 b, the switch 302(transistor) that drives by a driving signal applied by the timinggenerating unit 28, the sampling capacitor 303 to release fluctuationsby separating from a power supply, and the pixel equivalent circuit 304.

According to the first modification of the first embodiment of thepresent disclosure described above, it is possible to generate areference signal that has a fluctuation component in phase with animaging signal generated by the pixel 230, and that is used forcorrection processing of the imaging signal to be output to the A/Dconverter 27, and is possible to reduce a chip area in the imagingdevice 21.

Second Modification of First Embodiment

Next, a second modification of the first embodiment of the presentdisclosure is described. The second modification of the first embodimentdiffers in a configuration of the reference-signal generating unit 26according to the first embodiment. In the following, a configuration ofa reference-signal generating unit according to the second modificationof the first embodiment is described. Note that like reference symbolsare assigned to like components as the endoscope system 1 according tothe first embodiment described above, and description thereof isomitted.

Configuration of Reference-Signal Generating Unit

FIG. 13 is a circuit diagram schematically illustrating a configurationof the reference-signal generating unit according to the secondmodification of the first embodiment of the present disclosure.

A reference-signal generating unit 26 b illustrated in FIG. 13 has aconfiguration in which the switch 302 (transistor), the samplingcapacitor 303 (capacitor), the pixel equivalent circuit 304, thenoise-removal equivalent circuit 305, the column equivalent circuit 306,and the buffer equivalent circuit 307 are omitted from thereference-signal generating unit 26 according to the first embodimentdescribed above, and includes the resistance divider circuit 301constituted of two resistors 301 a and 301 b.

According to the second modification of the first embodiment of thepresent disclosure described above, it is possible to generate areference signal that has a fluctuation component in phase with animaging signal generated by the pixel 230, and that is used forcorrection processing of the imaging signal to be output to the A/Dconverter 27, and is possible to reduce a chip area in the imagingdevice 21.

Second Embodiment

Next, a second embodiment of the present disclosure is described. Thesecond embodiment differs in a configuration of the imaging device 21according to the first embodiment described above. In the following,after describing a configuration of an imaging device according to thesecond embodiment, an operation of the imaging device according to thesecond embodiment is described. Note that like reference symbols areassigned to like components as the endoscope system 1 according to thefirst embodiment described above, and description thereof is omitted.

Configuration of Circuit of Imaging Device

FIG. 14 is a circuit diagram schematically illustrating a configurationof the imaging device according to the second embodiment of the presentdisclosure. An imaging device 21 a illustrated in FIG. 14 includes abuffer unit 25 a and a reference-signal generating unit 26 c, in placeof the buffer unit 25 and the reference-signal generating unit 26 of theimaging device 21 according to the first embodiment described above.

Configuration of Buffer Unit

First, a configuration of the buffer unit 25 a is described. The bufferunit 25 a forms a voltage follower circuit along with the columnsource-follower buffers 244 connected thereto, which are sequentiallyselected by the horizontal scanning unit 245, amplifies an input imagingsignal to one time as large by the voltage follower, to output to theA/D converter 27. The buffer unit 25 a includes a first global circuit260 a and a second global circuit 270 a that are provided respectivelyfor an odd column and an even column of the pixels 230. The first globalcircuit 260 a and the second global circuit 270 a function as animpedance transforming unit.

The first global circuit 260 a includes a fourth transistor 266, aconstant-current power supply 267, a fourth transistor 266, aconstant-current power supply 267, a fifth transistor 268, and aconstant-current power supply 269, in addition to the configuration ofthe first global circuit 260 according to the first embodiment describedabove.

One end (source) of the fourth transistor 266 is connected to theconstant-current power supply 267, and the other end (drain) isconnected to the ground GND, and a gate is connected to the columnselecting switch 255 of the column source-follower buffer 244 throughthe first transistor 262 and the horizontal transfer line 257. Thefourth transistor 266 is configured using a PMOS.

One end of the constant-current power supply 267 is connected to thepower supply voltage VDD, and the other end is connected to one end(source) of the fourth transistor 266 and a gate of the fifth transistor268. In the second embodiment, the constant-current power supply 267functions as a constant-current power supply.

One end (drain) of the fifth transistor 268 is connected to the powersupply voltage VDD, the other end (source) is connected to theconstant-current power supply 269, and a gate is connected to theconstant-current power supply 267. The fifth transistor 268 isconfigured using NMOS.

One end of the constant-current power supply 269 is connected to theground GND, and the other end is connected to the other end (source) ofthe fifth transistor 268. In the second embodiment, the constant-currentpower supply 269 functions as a constant-current power supply.

The first global circuit 260 a thus configured has a source followerstructure in an output stage. Therefore, when the column source-followerbuffer 244 (column side circuit) sequentially selected by the horizontalscanning unit 245 is connected, the first global circuit 260 a forms avoltage follower circuit, and outputs an imaging signal (Vout) obtainedby amplifying an input imaging signal (Vin) to one time as large by thevoltage follower to the A/D converter 27.

The second global circuit 270 a has the same configuration as the firstglobal circuit 260 a described above, and includes the constant-currentpower supply 256, the switch 261, the first transistor 262, the secondtransistor 263, the third transistor 264, and the constant-current powersupply 265, the fourth transistor 266, the constant-current power supply267, the fifth transistor 268, and the constant-current power supply269.

The second global circuit 270 a thus configured forms a voltage followercircuit along with the column source-follower buffers 244 (column sidecircuit) of an even column connected thereto, which are sequentiallyselected by the horizontal scanning unit 245, and outputs an imagingsignal (Vout) obtained by amplifying an input imaging signal (Vin) toone time as large by voltage follower, to the A/D converter 27.

The reference-signal generating unit 26 c generates a reference signalhaving a fluctuation component in phase with an imaging signal generatedby the pixel 230 and used for correction processing of the imagingsignal, to output to the A/D converter 27. Details of a circuit of thereference-signal generating unit 26 c are described in FIG. 15 later.

Configuration of Reference-Signal Generating Unit

Next, a detailed configuration of the reference-signal generating unit26 c described in FIG. 14 is described. FIG. 15 is a circuit diagramschematically illustrating a configuration of a reference-signalgenerating unit 26 c.

The reference-signal generating unit 26 c illustrate in FIG. 15 includesa buffer equivalent circuit 307 a in place of the buffer equivalentcircuit 307 of the reference-signal generating unit 26 according to thefirst embodiment described above.

The buffer equivalent circuit 307 a forms a circuit equivalent to thefirst global circuit 260 a, and includes the constant-current powersupply 256, the switch 261, the first transistor 262, the secondtransistor 263, the third transistor 264, and the constant-current powersupply 265, the fourth transistor 266, the constant-current power supply267, the fifth transistor 268, and the constant-current power supply269. Because the buffer equivalent circuit 307 a is a circuit equivalentto the first global circuit 260 a described above, detailed descriptionthereof is omitted.

The reference-signal generating unit 26 c thus configured generates areference signal (VREF) having a fluctuation component in phase with theimaging signal generated by the pixel 230 and used for correctionprocessing of the imaging signal, to output to the A/D converter 27.

Operation of Imaging Device

Next, an operation of the imaging device 20 is described. FIG. 16A is atiming chart illustrating an operation of the imaging device 20. FIG.16B is a schematic diagram in which part of the timing chart in a regionR2 in FIG. 16A is enlarged. Referring to FIG. 16A, an explanation ismade about operations from reading an imaging signal from the pixel 230of a row <n> of the light receiving unit 23 through outputting a digitalimaging signal from the A/D converter 27. Note that, it is assumed thatonly one photoelectric converting device 231 is included in the pixel230 for convenience sake in the timing chart illustrated in FIG. 16A.When plural photoelectric converting device 231 s are included in thepixel 230 (in the case of shared pixel), an operation corresponding toone image signal line in this timing chart is repeated as many times asthe number of the photoelectric converting devices 231 included in thepixel 230. FIG. 16A illustrates, sequentially from the top most line,the driving signal ϕR, the driving signal ϕT, the driving signal ϕVCL,the driving signals SW21 to SW2 n, voltages VIN1 to VINn of the transfercapacitor 252, the output voltage Vout of the buffer unit 25 a,conversion timing of the A/D converter 27, the reference clock CLK,output timing of a conversion result of the A/D converter 27, and thereference signal VREF. Furthermore, FIG. 16B illustrates, sequentiallyfrom the top most line, the reference signal VREF, the output voltageVout of the buffer unit 25, the reference clock CLK, an operation modeof the A/D converter 27, and a difference obtained by subtracting thereference signal VREF from the output voltage Vout of the buffer unit 25a (Vout−VREF).

As illustrated in FIG. 16A and FIG. 16B, first, the timing generatingunit 28 turns on the clamp switch 253 (the driving signal ϕVCL is high),turns on the pixel resetting unit 236 (the pulsed driving signal ϕR<0>is high), and turns off the transfer transistor 234 (the pulsed drivingsignal ϕT<0> is low) (time T1). With this, a noise signal includingvariations specific to the pixel 230 to be read, a noise at the time ofpixel reset, and the like is output to the vertical transfer line 239from the pixel 230. At this time, by maintaining the on state of theclamp switch 253 (the driving signal ϕVCL is high), the gate of thecolumn source-follower transistor 254 of the column source-followerbuffer 244 is to be a voltage of the clamp voltage VCLP, and thetransfer capacitor 252 is charged with VRST-VCLP.

Next, the timing generating unit 28 turns on the transfer transistor 234(the pulsed driving signal ϕT<0> is high) while the clamp switch 253 isoff (the driving signal ϕVCL is low). With this, the charge convertingunit 233 reads out a charge-converted signal subjected to photoelectricconversion by the photoelectric converting device 231 to the verticaltransfer line 239 (time T2). In this state, an imaging signal VSIGsubjected to voltage conversion by the charge converting unit 233 istransferred to the vertical transfer line 239. By this operation, thetransfer capacitor 252 is charged with VCLP−(VRST1−VSIG1). Thus, theimaging signal (optical signal) from which a noise signal is removed isoutput to the gate of the column source-follower transistor 254 of thecolumn source-follower buffer 244 through the transfer capacitor 252.The signal output to the gate of the column source-follower transistor254 of the column source-follower buffer 244 is a signal sampled basedon the clamp voltage VCLP.

Subsequently, the timing generating unit 28 turns on the columnselecting switch 255 (the driving signal SW21 is high) (time T3), andthe imaging signal Vout (VCLP−(VRST1−VSIG1) charged in the transfercapacitor 252 is thereby output to the A/D converter 27 through thecolumn source-follower buffer 244 and the first global circuit 260 a.

Thereafter, the timing generating unit 28 switches the column selectingswitch 255 between on and off (the driving signal SW21 is low, thedriving signal SW22 is high) (time T4), and the imaging signal Vout(VCLP−(VRST2−VSIG2) charged in the transfer capacitor 252 is therebyoutput to the A/D converter 27 through the column source-follower buffer244 and the first global circuit 260 a. At this time, the A/D converter27 subjects the imaging signal Vout output from the transfer capacitor252 to A/D conversion based on the reference signal VREF output from thereference-signal generating unit 26, and outputs the digital imagingsignal D1 to the outside.

Subsequently, the timing generating unit 28 switches the columnselecting switch 255 between on and off sequentially (the drivingsignals SW22 to SW2 n) (time TN), the imaging signal Vout(VCLP−(VRSTn−VSIGn) charged in the transfer capacitor 252 is therebyoutput to the A/D converter 27 sequentially through the columnsource-follower buffer 244 and the first global circuit 260 a. At thistime, the A/D converter 27 subjects the imaging signal Vout sequentiallyoutput from the transfer capacitor 252 to A/D conversion based on thereference signal VREF output from the reference-signal generating unit26 c, and sequentially outputs the digital imaging signals D2 to DN tothe outside.

By repeating the operation as described above as many time as the numberof columns of the light receiving unit 23 (or as many times as thenumber of columns to be read), a digital imaging signal in which afluctuation component in phase with the imaging signal is cancelled isoutput to the outside. Furthermore, by repeating the reading operationfor one line as many times as the number of pixel rows (or as many timesas the number of rows to be read), the imaging device 20 outputs adigital imaging signal corresponding to one frame to the outside.

Moreover, as illustrated in FIG. 16B, while the reference signal VREFand the imaging signal Vout have a common mode noise, the difference(Vout−VREF) between the output voltage Vout of the buffer unit 25 andthe reference signal VREF is not influenced by the common mode noise.The A/D converter 27 samples the output voltage Vout input from thebuffer unit 25 and the reference signal VREF generated by thereference-signal generating unit 26 c at the same timing, and outputsthe digital imaging signal Vout to the outside. As a result, the A/Dconversion resultant is not influenced by the common mode noise.

According to the second embodiment of the present disclosure describedabove, the first global circuit 260 a serves as a voltage followercircuit when the column source-follower buffer 244 (column side circuit)of an odd column that is sequentially selected by the horizontalscanning unit 245 is connected to the first global circuit 260 a,performs impedance transformation with respect to a voltage of theimaging signal (Vin) input from the column source-follower buffer 244,amplifies the imaging signal to an amplification factor to one time byvoltage follower, and outputs the imaging signal (Vout). Therefore, itis possible to make the maximum use of a level of the imaging signaloutput by the column source-follower buffer 244.

Moreover, according to the second embodiment of the present disclosure,by structuring the first global circuit 260 a in a source follower,settling performance of the column source-follower buffer 244 can beimproved.

Furthermore, according to the second embodiment of the presentdisclosure, by structuring the first global circuit 260 a in a sourcefollower, the linearity can be maintained even when the inputcapacitance of the A/D converter 27 is increased.

Moreover, according to the second embodiment of the present disclosure,because the reference-signal generating unit 26 c generates a referencesignal having a fluctuation component in phase with an imaging signalthat is generated by the pixel 230, it is possible to convert theimaging signal into a digital imaging signal to be output, in acondition practically not influenced by a common mode noise.

Furthermore, according to the second embodiment of the presentdisclosure, because a capacitor connected to the input terminal of thecomparator circuit 403 can be made substantially flat, it is possible toprevent degradation of the linearity of an output signal that is outputby the A/D converter 27.

Third Embodiment

Next, a third embodiment of the present disclosure is described. Thethird embodiment differs in a configuration of the first A/D convertingunit 280 and the second A/D converting unit 290 in the A/D converter 27according to the first embodiment. In the following, configurations of afirst A/D converting unit and a second A/D converting unit aredescribed. Note that like reference symbols are assigned to likecomponents as the endoscope system 1 according to the first embodimentdescribed above, and description thereof is omitted.

Configuration of First A/D Converting Unit

FIG. 17 is a circuit diagram schematically illustrating a configurationof the first A/D converting unit according to the third embodiment.Because the first A/D converting unit and the second A/D converting unitaccording to the third embodiment have the same circuit configuration,only the configuration of the first A/D converting unit is described inthe following, and description of the configuration of the second A/Dconverting unit is omitted. Moreover, a first A/D converting unit 280 aillustrated in FIG. 17 is a successive approximation A/D converter andis an A/D converter of 9-bit output, but not limited thereto, the numberof output bit may be changed as appropriate.

The first A/D converting unit 280 a illustrated in FIG. 17 includes acorrection circuit 406 in place of the correction circuit 404 of thefirst A/D converting unit 280 according to the first embodimentdescribed above.

The correction circuit 406 cancels a stray capacitance of the inputtransistor of the comparator circuit 403, and thereby corrects a pair ofanalog signals input to the comparator circuit 403. The correctioncircuit 406 includes the correction transistor 404 a that cancels astray capacitance of the input transistor of the comparator circuit 403,and a bias circuit 406 b that applies the bias voltage VB to thecorrection transistor 404 a, and that can adjust the bias voltage VB.The bias circuit 406 b is configured using, for example, a variableresistor, or the like. The bias circuit 406 b may be configured using anoutput signal of the DAC circuit.

Method of Adjusting Bias Voltage VB of Correction Circuit

Next, a method of adjusting a bias voltage of the correction circuit 406illustrated in FIG. 17 is described. FIG. 18 is a flowchart illustratinga method of adjusting a bias voltage of the correction circuit 406. FIG.19A to FIG. 19C are diagrams schematically illustrating an INLcharacteristic (9-bit ADC) when the bias voltage (n) of the correctioncircuit 406 is changed. In FIG. 19A to FIG. 19C, a horizontal axisrepresents code, and a vertical axis represents INL[a.u]. Moreover, acurve L41 in FIG. 19A represents an INL characteristic of bias voltageVB=VB(1), a curve L42 in FIG. 19B represents an INL characteristic ofbias voltage VB=Vb(N), and a curve L43 in FIG. 19C represents an INLcharacteristic of bias voltage VB=VB(n).

As illustrated in FIG. 18, first, the user adjusts the bias circuit 406b and sets a value of the bias voltage VB(1) to VB(N) (step S101), andsets n=1 (step S102). N represents the maximum value when the biasvoltage VB is divided.

Subsequently, the bias circuit 406 b applies the bias voltage VB(n) tothe correction transistor 404 a (step S103).

Thereafter, the user inputs a test signal to the first A/D convertingunit 280 a to cause A/D conversion (step S104), measures an output codeDOUT(n) that is output from the first A/D converting unit 280 a, tocalculate INL(n) (step S105). In this case, the INL characteristic ofthe bias voltage VB(1) forms an upward convex shape as shown in thecurve L41 in FIG. 19A.

Subsequently, the user calculates, from the calculated INL(n), themaximum value INL_MAX(n) of INL and the minimum value INL_MIN(n) (stepS106).

Thereafter, the user determines whether n is N (step S107). When n is N(step S107: YES), it shifts to step S109 described later.

On the other hand, when n is not N (step S107: NO), the user incrementsn to (n=n+1) (step S108), and returning to step S103, steps S102 to S107described above are repeated unit n=N is obtained. In this case, the INLcharacteristic of the bias voltage VB(N) forms a downward convex shapeas shown in the curve L42 in FIG. 19B.

At step S109, the user selects n for which a difference between absolutevalues of the maximum value INL_MAX(n) and the minimum value INL_MIN(n)is small, and an average value of absolute values of the maximum valueINL_MAX(n) and the minimum INL_MIN(n) is small.

Thereafter, the user sets the bias voltage VB(n) as a bias voltage ofthe correction transistor 404 a (step S110). Specifically, the useradjusts such that the bias voltage applied to the correction transistor404 a by the bias circuit 406 b is to be VB(n). In this case, asillustrated in FIG. 19C, the INL characteristic of the bias voltageVB(n) forms a substantially straight line as shown in the curve L43 inFIG. 19C. After step S110, the user ends this processing.

According to the third embodiment of the present disclosure describedabove, because a capacitor connected to the input terminal of thecomparator circuit 403 can be made substantially flat, it is possible toprevent degradation of the linearity of an output signal that is outputby the A/D converter 27.

Other Embodiments

In the embodiments of the present disclosure, an imaging signalgenerated by an imaging device is transmitted to a processor through atransmission cable, but it does not need to be wired transmission, forexample, and it may be wireless communication. In this case, the imagingsignal can be transmitted to the processor by a predetermined wirelesscommunication standard (for example, Wi-Fi (registered trademark) orBluetooth (registered trademark)). The wireless communication may beperformed also by other wireless communication standards, of course.Furthermore, besides the imaging signal, update information to updatevarious kinds of information of an endoscope may be transmitted.

Moreover, in the embodiments of the present disclosure, an imagingdevice is configured in one chip. However, two chips may be used. Inthis case, one is a pixel chip in which multiple pixels are arranged andthe other is a circuit chip in which various kinds of circuits from areading unit to an A/D converter are arranged. Additionally, the circuitchip may be stacked on the pixel chip.

Furthermore, in the embodiment of the present disclosure, a digitalimaging signal is transmitted to the connector unit from the A/Dconverter through a transmission cable, but by arranging, for example,an optical coupler that converts the digital imaging signal into anoptical signal, or the like, the digital imaging signal may betransmitted to the connector unit as the optical signal.

Moreover, in the present application, operations have been describedusing terms of “first”, “next”, “subsequently”, “thereafter”, and thelike for convenience in description of the flowchart of variousoperations described above, but it is not intended that the operationsare required to be performed in this order.

Furthermore, in the embodiments of the present disclosure, the processorand the light source device are formed in one piece, but not limitedthereto, for example, the processor and the light source device may bearranged separately.

Moreover, the embodiments of the present disclosure have been describedusing a simultaneous endoscope as an example, but it is applicable alsoto a frame sequential endoscope.

Furthermore, the embodiments of the present disclosure are applicablenot only to a soft endoscope (vertical endoscope), but also to a hardendoscope, a sinus endoscope, and an endoscope system including anelectrosurgical knife and an inspection probe, and the like.

Furthermore, the embodiments of the present disclosure have beendescribed using an imaging device of an endoscope in which a successiveapproximation A/D converter is arranged at a distal end of an insertionportion to be inserted into a subject as an imaging device as anexample, but it is not limited thereto. It is applicable to an imagingdevice in which a lens unit is detachable, an imaging device in whichmobile phone is integrated, an imaging device without a display monitor,a surveillance camera operated through a network, an imaging device usedfor a digital camcorder and a microscope.

Moreover, the present disclosure is not limited to the embodiments andthe modifications described above as they are. In a practical phase, itcan be implemented by changing components within a range not departingfrom the gist of the disclosure. Furthermore, by combining thecomponents disclosed in the embodiments described above, variousdisclosures can be formed. For example, some of the components out ofall of the components described in the embodiments and the modificationsdescribed above can be deleted. Moreover, the components described inthe embodiments and the modifications can be combined as appropriate.

Furthermore, a term that is described with a different broader orsynonymous term at least once in the specification of in the drawingscan be replaced with the different term in any part of the specificationor the drawings. As described, various modifications and applicationsare enabled within a range not departing from the gist of thedisclosure.

According to the present disclosure, an effect of preventing degradationof linearity of an output signal is obtained.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the disclosure in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

What is claimed is:
 1. A successive approximation analog-to-digitalconverter comprising; a sampling circuit configured to sample a pair ofanalog signals input as a differential input signal; a capacitor circuitthat has a binary capacitance configured to hold the pair of analogsignals sampled by the sampling circuit, the capacitor circuit beingconfigured to reflect a signal level of a reference signal to the pairof analog signals through the binary capacitance to generate a pair ofvoltage signals; a comparator circuit that includes an input transistorto which the pair of voltage signals are input, the comparator circuitbeing configured to compare one of the pair of voltage signals with theother signal of the pair of voltage signals; a correction circuit thatis provided in a previous stage to the comparator circuit, thecorrection circuit being configured to output the pair of voltagesignals in which voltage dependency of stray capacitance in the inputtransistor is cancelled to the comparator circuit; and a control circuitconfigured to successively determine a value of each bit of a digitalsignal corresponding to the binary capacitance based on a comparisonresult by the comparison circuit, and to reflect the value of each bitof the digital signal to the reference signal.
 2. The successiveapproximation analog-to-digital converter according to claim 1, whereinthe correction circuit includes a correction transistor configured tocancel the voltage dependency of the stray capacitance; and a biascircuit configured to apply a predetermined bias voltage to thecorrection transistor.
 3. The successive approximation analog-to-digitalconverter according to claim 2, wherein the bias circuit is configuredto adjust the bias voltage.
 4. The successive approximationanalog-to-digital converter according to claim 3, wherein a voltagedependence of a capacitance of the correction transistor is inverse to avoltage dependence of the stray capacitance.
 5. An imaging devicecomprising: the successive approximation analog-to-digital converteraccording to claim 1; an imaging device including a plurality of pixelsthat are arranged in a two-dimensional matrix, and that receive lightinput from outside to perform photoelectric conversion, and that outputsan imaging signal, wherein the imaging device includes a noise removingcircuit that is arranged for each of columns of the two-dimensionalmatrix in which the pixels are arranged, the noise removing circuitbeing configured to remove a noise component included in the imagingsignal; a plurality of column source-follower buffers that are arrangedfor each of the columns of the two-dimensional matrix in which thepixels are arranged, the plurality of column source-follower buffersbeing configured to and that amplify the imaging signal from which thenoise component is removed by the noise removing unit; a columnselecting circuit that sequentially selects the column source-followerbuffers to output the imaging signal; and a buffer circuit that forms avoltage follower circuit, being connected to the column source-followerbuffer sequentially selected by the column selecting circuit, and thatsubjects a voltage of the imaging signal output from the columnsource-follower buffer to impedance transformation, to output to thesuccessive approximation analog-to-digital converter.
 6. The imagingdevice according to claim 5, wherein the imaging device further includesa reference-signal generating circuit that generates a reference signalincluding a fluctuation component in phase with the signal generated bythe pixel, to output to the successive approximation analog-to-digitalconverter, and the successive approximation analog-to-digital converteraccepts the imaging signal and the reference signal as the differentialinput signal.
 7. The imaging device according to claim 6, wherein thereference-signal generating circuit includes any one of a device and acircuit having a structure equivalent to the pixel.
 8. An endoscopecomprising: an imaging device according to claim 5; and an insertionportion insertable to a subject, the insertion portion includes theimaging device at a distal end.
 9. A setting method that is performed ina successive approximation analog-to-digital converter having acorrection circuit that includes a sampling circuit that samples a pairof analog signals input as a differential input signal; a capacitorcircuit that has a binary capacitance holding the pair of analog signalssampled by the sampling circuit, the capacitor circuit being configuredto reflect a signal level of a reference signal to the pair of analogsignals through the binary capacitance to generate a pair of voltagesignals; a comparator circuit that includes an input transistor to whichthe pair of voltage signals are input, the comparator circuit beingconfigured to compare one of the pair of voltage signals with the othersignal of the pair of voltage signals; a correction transistor that isprovided in a previous stage to the comparator circuit, the correctiontransistor being configured to cancel voltage dependency of straycapacitance in the input transistor; and a bias circuit that applies apredetermined bias voltage to the correction transistor, the correctioncircuit being configured to output the pair of voltage signals to thecomparator circuit; and a control circuit configured to successivelydetermine a value of each bit of a digital signal corresponding to thebinary capacitance by binary search, based on a comparison result by thecomparator circuit, and to reflect the value of each bit of the digitalsignal to the reference signal, the method comprising: setting a valueof the bias voltage applied by the bias circuit; applying the biasvoltage having the set value sequentially to the correction transistor;inputting a test signal to the successive approximationanalog-to-digital converter sequentially such that the successiveapproximation analog-to-digital converter is caused to performanalog-to-digital conversion; calculating an integral non-linearitydifference of each of the output code based on a measurement resultobtained by sequentially measuring the output code converted at theanalog-to-digital conversion; calculating respective maximum value andminimum value of the integral non-linearity difference for each of theoutput code, based on the integral non-linearity difference; and settinga value of the bias voltage such that a difference between absolutevalues of the calculated maximum values and the calculated minimumvalues is reduced, and such that an average value of the absolute valuesof the maximum values and the minimum values is reduced, as a value ofthe bias voltage to be applied by the bias circuit.